Short answer: Cat qubits store quantum information in an oscillator so that bit-flip errors are suppressed exponentially as the photon number grows, leaving phase flips to correct. That can cut the hardware overhead of error correction. Papers from 2023 to 2025 report a squeezed-cat design with lower bit-flip rates, a stabilised cat qubit with bit-flip times above 0.1 seconds, and a logical memory that combines cat qubits with a distance-5 repetition code. These are laboratory results.
Why cat qubits
A 2025 Nature paper states that quantum computers probably need error correction, with a logical qubit redundantly encoded in many noisy physical qubits, and that the large physical-qubit overhead motivates more hardware-efficient approaches. A 2023 Physical Review A paper says noise-biased qubits are a promising route to significantly reduce that overhead. A 2024 arXiv paper describes cat qubits as a type of bosonic qubit in a harmonic oscillator that can show an exponential noise bias against bit-flips as the mean photon number rises.
Squeezed cat codes
The 2023 paper analyses a dissipatively stabilised squeezed-cat qubit, a nonlocal encoding in phase space based on squeezed coherent states with exponential error bias. The authors find that for moderate squeezing the bit-flip rate is significantly lower than for the ordinary cat qubit while the phase-flip rate is unchanged, and that squeezing allows faster, higher-fidelity gates. The paper explains that, in the large-squeezing and large-displacement limits, the squeezed-cat code can approximately satisfy the Knill-Laflamme conditions for both single-photon loss and dephasing, merging features of cat and GKP codes.
Building a better stabilised cat qubit
The 2024 paper focuses on cat qubits stabilised by two-photon dissipation, where pairs of photons are added and removed from the oscillator by an auxiliary lossy buffer mode. The process needs a large loss rate and strong nonlinearities in the buffer without degrading the oscillator. The authors colour the loss environment of the buffer with a multi-pole filter and optimise the circuit for extra inductances. They report near-ideal growth of the bit-flip time with photon number, reaching over 0.1 seconds with a mean photon number of only 4, while phase-flip behaviour corresponds to an effective lifetime of about 70 microseconds, comparable to the bare oscillator. They keep this performance with an ancilla transmon used for readout by engineering a tunable oscillator-ancilla coupling.
A logical memory with cat qubits
The 2025 Nature paper realises a logical qubit memory in a superconducting circuit by concatenating cat qubits with an outer repetition code of distance 5. A stabilising circuit passively protects the cat qubits from bit flips, and the repetition code, using ancilla transmons for syndrome measurement, corrects phase flips. The authors find the phase-flip correction operates below threshold, and logical bit-flip errors fall as the cat photon number increases, enabled by a cat-transmon noise-biased CX gate. The minimum measured logical error per cycle is 1.75 percent on average for distance-3 sections and 1.65 percent for distance-5, and they note the high noise bias lets the larger code perform comparably despite more fault locations.
What this does not tell you
The logical error per cycle is still above one percent, and this is a memory, not a computation. The 2023 result is a theoretical analysis, and the different papers use different devices.
FAQ
What is a cat qubit?
A qubit encoded in an oscillator whose bit-flip errors are suppressed as photon number grows.
Why does that save hardware?
Only phase flips need correcting, so a simple repetition code can be used.
How long can bit-flips be suppressed?
A 2024 paper reports bit-flip times above 0.1 seconds at a mean photon number of 4.
What was the logical error rate?
About 1.65 to 1.75 percent per cycle in the 2025 memory experiment.
Is this a full processor?
No. It is a logical memory demonstration.
All field notes