The heavy-hex lattice qubit layout

Short answer: The heavy-hex lattice is the qubit layout IBM Quantum used for its devices from August 2021, in which each unit cell is a hexagon of qubits with an extra qubit on each edge. IBM's own 2021 blog says the lower connectivity reduces frequency collisions and spectator errors. A 2020 Physical Review X paper from IBM researchers describes error-correcting codes designed for this kind of layout. The performance statements come from the vendor and are not independently checked here.

The layout

IBM's July 2021 blog post says that as of 8 August 2021 the topology of all active IBM Quantum devices would be based on the heavy-hex lattice, the fourth iteration of its topology and the basis for the Falcon and Hummingbird processor architectures. Each unit cell is a hexagonal arrangement of qubits with an additional qubit on each edge. IBM says it was retiring its square and bow-tie topologies in favour of it. The post describes the topology as a product of co-design between experiment, theory and applications, and says it is a slight reduction in qubit connectivity from earlier systems.

Why lower connectivity

IBM's systems use fixed-frequency qubits, whose properties are set at fabrication, and the two-qubit gate is the cross-resonance gate, where the control qubit is driven at the target qubit's resonance frequency. IBM says these frequencies must be off-resonant with neighbouring qubits' transition frequencies to prevent undesired interactions it calls frequency collisions. The larger the connectivity, the more frequency conditions must be satisfied and the more likely degeneracies become.

The post says the lower connectivity and the chosen pattern of control and target frequencies give an order of magnitude increase in the yield of devices with zero frequency collisions compared with other topologies, based on simulations it shows in a figure. It also says sparsity reduces spectator errors, which are errors from qubits not taking part in a given two-qubit gate. These are IBM's claims about its own design.

Codes for low-degree graphs

The 2020 Physical Review X paper by Chamberland, Zhu, Yoder, Hertzberg and Cross, all at IBM, introduces the heavy-hexagon code and the heavy-square code. Both assign data and ancilla qubits to the vertices and edges of low-degree graphs, a layout the authors say suits superconducting architectures by minimizing frequency collisions and cross talk, with collisions reduced by several orders of magnitude in some cases. The heavy-hexagon code is a hybrid surface and Bacon-Shor code on a heavy-hexagonal lattice, and the heavy-square code is the surface code on a heavy-square lattice.

The authors say the limited connectivity might naively limit error-correcting capability, so flag qubits are essential to the construction. They modify minimum-weight perfect-matching decoding to use the flag measurements and correct up to the full code distance within the limited connectivity. They report that simulations show high threshold values for both codes and say the decoding scheme can be adapted to other topological code families.

Limits

Both of the main pages are from IBM or its researchers. The blog is a corporate technical post and its device error-rate claims are not independently verified here. The paper's threshold results are from simulation.

FAQ

What is the heavy-hex lattice?

According to IBM, a unit cell is a hexagon of qubits with an additional qubit on each edge.

Which processors use it?

IBM says it is the basis for the Falcon and Hummingbird architectures.

Why did IBM reduce connectivity?

IBM says it reduces frequency collisions and spectator errors that hurt application performance.

Is it used for error correction?

The 2020 paper introduces the heavy-hexagon code for this kind of layout, with simulated thresholds, and uses flag qubits to respect the limited connectivity.

Are IBM's performance claims independent?

No, they are IBM's own statements.