Short answer: Fixed-frequency transmon qubits need their frequencies set precisely, but the Josephson junction at the heart of each qubit varies in area and tunnel barrier from junction to junction. That variation shows up as qubit frequency spread and possible frequency collisions between neighbours. Papers from 2020, 2021 and 2026 report wafer-scale junction processes with resistance variation of a few percent and post-fabrication tuning that narrows it further. These are fabrication results from research devices.
Why variation matters
A 2020 paper in Superconductor Science and Technology describes the transmon as a Josephson junction acting as a non-linear inductor, shunted by a capacitor to form an anharmonic oscillator, with a coherent lifetime of order 100 microseconds for a robust device. In a complex device with many transmons, precise control of each qubit frequency is often required, so variations in junction area and tunnel barrier thickness must be minimised to avoid spectral overlap between neighbouring circuits. A 2026 Scientific Reports paper puts it the same way: resistance fluctuations translate into qubit-frequency dispersion and potential frequency collisions, which remains a central challenge in scaling fixed-frequency architectures.
Wafer-scale uniformity in 2020
The 2020 authors found that moving a recipe optimised for single stand-alone devices to a wafer, producing 64 dies of 1 by 1 cm from a 150 mm wafer, initially produced global drifts of plus or minus 30 percent in room-temperature tunnelling resistance. Through a systematic study of 38 wafers they developed a process giving under 3.5 percent relative standard deviation in critical current, inferred from resistance, for 3000 junctions across 49 square centimetres. Their best process, which uses ultrasonically assisted development, uniform ashing and dynamic oxidation, gave 1.8 percent within a 1 by 1 cm window on average, with a few windows under 1 percent.
A 2021 study of more than 3600 junctions
A 2021 Applied Physics Letters paper reports an average resistance variation of 3.7 percent across a wafer holding forty 0.5 by 0.5 cm chips, falling to an average on-chip value of 2.7 percent. For the junction sizes used in fixed-frequency transmons, 0.02 to 0.06 square micrometres, it found wafer-level resistance variation of 3.4 to 4.9 percent, corresponding to 1.7 to 2.5 percent in qubit frequency. It attributes 60 to 70 percent of the variation to junction-area fluctuations and the rest to tunnel-junction inhomogeneity, and measures an average quality factor of 1.6 million for qubits, without additional losses compared with the authors' standard process.
Tuning after fabrication in 2026
The 2026 paper combines large-area process control on 200 mm wafers with chip-level electrical fine-tuning. Within a central 80 by 80 mm field, its Manhattan-style aluminium junction process gave relative standard deviations of 5.1 to 5.2 percent in junction area and 5.8 to 7.2 percent in room-temperature resistance. Alternating-bias assisted annealing reduced chip-level resistance variation to 1.3 percent on a chip with all 20 junctions tuned, and to 1.7 percent for 16 tuned junctions in a cryogenically characterised 20-qubit chip. In a cross-chip comparison, the coherence distributions of the treated chip and an untreated reference overlapped. The authors conclude that large-area feed-forward correction and post-fabrication tuning can improve junction repeatability in fixed-frequency circuits.
What this does not tell you
Different papers use different wafers, areas and metrics, so their percentages are not directly comparable. Resistance variation is a proxy for frequency variation. None of this shows a large processor free of frequency collisions.
FAQ
Why does junction variation matter?
Resistance spread translates into qubit frequency spread, which can cause collisions between neighbouring qubits.
How uniform can junctions be?
The 2020 paper reports under 3.5 percent critical-current variation across 49 square centimetres, and 1.8 percent within 1 by 1 cm.
What causes the variation?
A 2021 study attributes 60 to 70 percent of it to junction-area fluctuations.
Can junctions be tuned afterwards?
A 2026 paper reports annealing that cut chip-level resistance variation to about 1.3 to 1.7 percent.
Did tuning hurt coherence?
In that paper's comparison, the coherence distributions of treated and untreated chips overlapped.
All field notes