Hook Errors and Syndrome Extraction Schedules in the Surface Code

Short answer: Hook errors are faults on an auxiliary qubit part-way through syndrome extraction that spread to two data qubits, and a poor measurement schedule can halve the effective distance of a surface code. Three recent papers, two of them arXiv preprints, propose schedules or layouts that avoid this. They report results from numerical simulation and not from hardware.

What is a hook error?

The 2026 arXiv abstract on a diagonal schedule defines hook errors in the rotated surface code as errors on auxiliary qubits midway through syndrome extraction that propagate to correlated two-qubit data errors. If the extraction schedule is poorly chosen, these can reduce the circuit-level code distance by a factor of two. A second preprint says hook errors are a major challenge for logical operations in the surface code because they can reduce the fault distance below the code distance.

What did the diagonal schedule propose?

The traditional approach uses N-shaped and Z-shaped schedules and picks the orientation in each plaquette so hook errors do not align with logical operators. The authors say this becomes complex within lattice surgery primitives with varied boundary geometries and needs a 7-step schedule to avoid gate collisions. They propose a diagonal schedule that orients hook errors along the diagonal of each plaquette, so the errors never align with logical operators regardless of boundary orientation and full code distance is achieved. The schedule is globally uniform, with one schedule for all X-type plaquettes and another for all Z-type ones. On hardware that supports parallel measurement, reset and gate operations, they report a minimal period of 6 time steps compared with 7 for the traditional approach. They demonstrate it for memory experiments, spatial junctions, spatial Hadamard gates and patch rotation in simulation, showing equivalent or improved logical error rates.

What did the ZX interleaving paper propose?

A separate 2026 preprint says existing methods either increase circuit depth or need simultaneous execution of measurements and CNOT gates, which adds overhead and lowers the threshold. The authors propose ZX interleaving syndrome extraction, which they say preserves the full fault distance d for any surface-code layout with regular stabilizer tiles at minimum depth, meaning four layers of CNOT gates. The idea is to interleave Z and X stabilizer tiles so hook-error edges in the decoding graph are shortened and effectively eliminated. Numerical simulations under uniform depolarizing noise for memory and lattice-surgery experiments confirm a full fault distance of d, whereas the best existing minimum-depth approach reaches d minus 1. The authors say the method may serve as an indispensable technique for practical fault-tolerant computing, which is their own assessment.

How do hook errors matter for dense packing?

A Physical Review journal paper studies dense packing of surface-code patches, which has been proposed to reduce the number of physical qubits per logical qubit to about three-fourths of side-by-side patches. The authors present a code-deformation procedure and a conceptual microarchitecture, plus a CNOT scheduling that suppresses hook errors. In circuit-level Monte Carlo simulation, the logical error rate of the densely packed code falls below that of the standard surface code as the code distance grows and the physical error rate falls, and they find this happens only with hook-error-avoiding syndrome extraction.

How to read this

All results are simulations, under particular noise models, and the three papers use different layouts and conditions. The two preprints may change before peer review. This post is based on abstracts and visible summary text and full texts were not checked. It makes no claim about built systems.

FAQ

Why do hook errors reduce distance?

They create correlated two-qubit data errors that can align with a logical operator, which lowers the effective distance, according to the diagonal-schedule abstract.

What is the diagonal schedule's advantage?

A uniform schedule that avoids geometry-dependent planning and needs 6 time steps instead of 7 on suitable hardware, per its authors.

What is full fault distance?

The ZX interleaving paper uses it to mean the fault distance equals the code distance d, which it reports achieving at four CNOT layers.

Has any of this run on hardware?

Not in these abstracts, which describe numerical simulation.